APA (7th ed.) Citation

Vrbický, A., Donoval, D., & Marek, J. TEMPERATURE ANALYSIS OF THE RUGGEDNESS OF POWER MOS TRANSISTOR DURING UIS TEST SUPPORTED BY MODELING AND SIMULATION.

Chicago Style (17th ed.) Citation

Vrbický, Andrej, Daniel Donoval, and Juraj Marek. TEMPERATURE ANALYSIS OF THE RUGGEDNESS OF POWER MOS TRANSISTOR DURING UIS TEST SUPPORTED BY MODELING AND SIMULATION.

MLA (9th ed.) Citation

Vrbický, Andrej, et al. TEMPERATURE ANALYSIS OF THE RUGGEDNESS OF POWER MOS TRANSISTOR DURING UIS TEST SUPPORTED BY MODELING AND SIMULATION.